module insn_memory(
input [31:0] read, //address of read data. 32-bit
output [31:0] rd //read data
);

reg [31:0] insn [0:15];
initial begin
//initializing..//
insn[0] = {32'b000000_10010_10000_10010_00000_100000};
insn[1] = {32'b000000_10010_10010_01000_00000_100000};
insn[2] = {32'b000000_01000_01000_01000_00000_100000};
insn[3] = {32'b000000_01000_10011_01001_00000_100000};
insn[4] = {32'b101011_01001_10010_00000_00000_000000};
insn[5] = {32'b000100_10010_10001_00000_00000_000001};
insn[6] = {32'b000010_00000_00000_00000_00000_000000};
insn[7] = {32'b000000_10010_10001_10010_00000_100010};
insn[8] = {32'b000000_10010_10000_10010_00000_100000};
insn[9] = {32'b000000_10100_10010_10100_00000_100000};
insn[10] ={32'b000100_10010_10001_00000_00000_000001};
insn[11] ={32'b000010_00000_00000_00000_00000_100000};
insn[12] ={32'b101011_10011_11000_00000_00001_000100};
end

assign rd=insn[(read>>2)]; //reason to left-shift 2 : arry has 1-value difference between instructions

endmodule